A Quick Look at the TinyFGPA & Lattice Diamond

I’ve long since had an interest in the embedded world, particularly in FPGAs. So it’s been really exciting to see FPGAs making their way into the hobby electronics scene over the past few years. As an FPGA developer, aside from an HDL lab during my undergrad, I’ve been exclusive to the Xilinx family of FPGAs and their development IDE, Vivado (with which I have an on again-off again relationship with, but overall I think it’s a great tool).

However, most Xilinx development boards are on the higher end of the price scale for hobbyist (the barebones cheapest I could find was $80), and Vivado has quite the learning curve to it even for an experienced FPGA developer. Personally, I was looking to venture outside of my Xilinx bubble simply for the sake of learning something new and I wanted a quick/cheap way to get started.

Enter the TinyFPGA… For a whopping $12, I got myself the A1 model from TinyFPGA’s lineup. The TinyFPGA series are a great development board option for the Lattice Semi FPGA family. The A-series boards are equipped with chips from Lattice’s Mach chipset, the B-series boards are equipped with a chip from Lattice’s ICE series, and the newer TinyFPGA EX has one of Lattice’s ECP chips. For the A1 board, the MachXO2–256 offers the following respectable specs for such a tiny package (pun intended):

• 256 LUTs

• 2Kbit distributed RAM

• 18 dedicated IO

• 4 shared IO

• Internal flash memory

• Embedded function blocks for I2C, SPI, and timers

To get started, I first downloaded and installed the Lattice Diamond IDE. My hopes were high when the first tag line on Lattice’s download page was “Adapting to a new tool is hard. Lattice Diamond makes this easier…” The install was straightforward and Lattice will provide a free license file at request (they just want to make sure you’re just a hobbyist and not a business). Once installed and ready to go, I flipped over the the Github repository TinyFPGA has for the A-series and grabbed the .LPF file and template top level Verilog file for the A1 board. For those of you familiar with Xilinx, the .LPF file is the Lattice equivalent to an .XDC file in Vivado. This file is the constraints file for mapping external net names from the design to specific package pins on the device. The Verilog top file that TinyFPGA provides is a convenient starting point as it lines up some generic net names to the .LPF constraints file and has a top level module defined already.

Armed and ready, I created a new project in Lattice Diamond:

When importing the constraints file and top level Verilog file I got from TinyFPGA’s repo, I chose the option to copy a version into the file directory of this particular project. I strongly recommend always selecting this option because I can’t tell you how many times I’ve accidentally moved a source file I forgot were being referenced by other projects, thus breaking those projects…

The next window is just selecting the specific part targeted in the project, which I’ve highlighted the specific values for the A1 board.

Once moving forward to the next page, Lattices Diamond asks which synthesis tool to use for the project. I’m pretty sure the free license only includes the Lattice LSE synthesis tool, but regardless, this is Lattice’s baseline synthesis tool seems like the best place to start being new to the Lattice world. After verifying all of my settings on the summary screen, I had successfully created my first Lattice Diamond project. Under the File List tab in the left column, I opened up the top level Verilog file to start adding in my design.

The first place I always start with in any new FPGA design is my clock source which can be pretty different between device families, so I started poking through various datasheets for the MachXO2 on Lattice’s website. I discovered something pretty cool in the Lattice architecture, chips with logic densities of 1200 or greater can provide what Lattice refers to as ‘edge clocks’. This is simply a clock bridge at the outer edge of the package that allows for the FPGA to route a clock to a peripheral from its primary clock source with minimal skew. Since the TinyFPGA A1 only has a LUT count of 256, it doesn’t have this feature; if you’re interested in exploring this though, the A2 board does have a logic density of 1200. Cool artifacts aside, the MachXO2 devices are super simple to create a source clock for your design in, just instantiate an instance of the internal oscillator and pass a desired frequency in MHz to it, as well as the net name of the output reference clock. Due to the logic cell layout of the MachXO2 device, there are specific frequency values that the internal oscillator can support which can be found on page 29 of the MachXO2 sysCLOCK PLL Design and Usage Guide. The default and lowest frequency value is 2.08 MHz, and is what I’m going with for this first project. The standby pin is also something I will leave disabled (tied to ground) for this project since its functionality only serves during simulation. It is worth noting that this oscillator only has a +/- 5% accuracy, so you’ll need to provide an external clock from a tighter accuracy source if needed. For a good majority of hobby projects though, this internal oscillator within the device is more than sufficient.

With my clock source set and ready to go, I decided that I wanted to go for something a little more than just a blinking LED. Now don’t get me wrong, a blinking LED project is always a valuable tool for getting to know a new development IDE or new hardware, but since Lattice really followed through with their promise of how easy their IDE is, it felt appropriate to go a little bigger. After digging through my parts bins for ideas, I decided on a 7-segment display counting from 0–9 at a one second interval. Since my reference clock is 2MHz, I knew I needed to count out 2,000,000 for my one second interval which was a 21-bit register. Then I tacked on an extra 4 bits at the MSB to count from 0–9. Overall, I ended up with my top level Verilog file looking like this:

To synthesis the design and create all necessary output files, I found the quickest way was to flip over to the Process tab in the left hand column and right click on the ‘Export Files’ option, then select the ‘Rerun All’ option. Once this has completed, I verified that there were no errors or critical warnings (I had a couple of warnings just because I wasn’t utilizing a few things like the standby pin on the oscillator, but these are pretty low level warnings that one can usually ignore) then I right-clicked on the LEDEC file option and selected ‘Run’ to create my bitstream to flash onto the A1 board. Lattice’s file type for their bitstream files is .JED and it is output to .//impl/project_name_impl1.jed

With the digital design complete, I moved on to the hardware setup for this project. I utilized a standard 3.3V regulator with a USB breakout board to supply power to my A1 board (not forgetting a current-limiting resistor since I had the USB cable plugged into a 5V/1A wall plug). I also had an LED on pin 7 and left pin 7’s default functionality in my digital design as its default functionality serves as a programming status indicator. When you first power on a board that has nothing in its internal flash, this status LED will illuminate solid. While programming, the LED will flash, then extinguish to indicate programming is complete. I then wired up my 7-segment LED and I was ready to flash my bitstream onto the board.

I also chose to invest $9 to get TinyFPGA’s dedicated programmer that programs the board over the JTAG interface using a Python GUI that you can also grab a release of from TinyFPGA’s Github repository. This GUI utilizes a serial interface to do this, which you’ll need to install a virtual serial driver if you’re running a Windows version earlier than Windows 10.

After installing the TinyFPGA Programming Application (Python GUI), I plugged the power supply to my A1 board and connected the JTAG programmer.

The programming application will look for the COM port that the TinyFPGA board is on, and once it is decided, simply select the bitstream file and click ‘Program FPGA.’

And that’s it! A new board and a new IDE tackled in one project! I have to say, I am really impressed with how easy and intuitive Lattice Diamond was to pick up and navigate. I definitely recommend it to those of you that are new to the FPGA world. Same goes for the TinyFPGA board. Kudos to Luke Valenty! He really brought a valuable asset to the hobby FPGA community with the TinyFPGA.